1. Technical Field
The present invention generally relates to semiconductor memories and more particularly to a bipolar random access memory constructed of bipolar transistors.
2. Description of Related Art
Random access memories (RAM) used in buffer memories are required to have a particularly high operational speed, and for this reason, constructed of bipolar transistors. In such a RAM, reading and writing are carried out by flowing (passing) a read current and a write current to a selected memory cell via a selected word line and further through a selected bit line. In order to increase the operational speed, particularly of the writing speed of the memory, it is essential as well as desirable to increase the write current flowing from the selected bit line passing through the selected cell at the time of writing. By increasing the write current as such, transition of a bipolar transistor which forms a flip-flop circuit in the memory cell together with another bipolar transistor from a turn-off state to a turn-on state occurs in a reduced time, and the memory cell changes its state quickly.
FIGS. 1 and 2 show the typical construction and operation of a prior art bipolar random access memory. Referring to FIG. 1, the memory comprises a cell region 1 including a number of memory cells for storing cell information arranged in row and column formation and a control part 2 for controlling the reading and writing of cell information. In the cell region 1, a number of word lines WL1-WLn are connected to an address decoder 3, and the address decoder 3 sets the logic level of a desired word line to a level H in response to an address signal supplied thereto. When the level of the word line WL1 is changed to the level H for example, reading and writing of cell information becomes possible for a group of cells S11-S1n connected commonly to the word line WL1 via a pair of adjacent bit lines selected from a group of bit lines BL1-BLn. As already noted, each of the cells includes a flip-flop circuit of bipolar transistors.
Next, the bipolar memory of FIG. 1 will be described. As can be seen in FIG. 1, the cells are arranged in the cell region 1 in the form of a number of columns C1-Cn. For example, the column C1 includes cells S11, S21, etc. As each of the columns C1-Cn have an identical construction, only the column C1 will be described hereinafter and descriptions for the other columns will be omitted.
Referring to FIG. 1, transistors Tr1, Tr2, Tr3 and Tr4, each having its own emitter together with a common base and a common collector, are connected to bit lines BL1 and BL2 for bit line selection, and these transistors Tr1, Tr2, Tr3 and Tr4 are operated simultaneously in response to a bit line selection signal supplied to an input terminal BS1 from a column decoder not illustrated. Further, there are provided a pair of transistors Tr5 and Tr6 having emitters connected respectively to the bit line B11 and the bit line BL2 and bases connected respectively to emitters of transistors Tr26 and Tr27 to be described later. Further, another pair of transistors Tr7 and Tr8 are provided such that bases thereof are connected to the bit lines Bl1 and BL2 respectively and emitters thereof are connected commonly to a transistor Tr9 which is operated in response to the foregoing bit line selection signal to the input terminal BS. When the transistor Tr9 is turned on, the transistors Tr7 and Tr8 supply voltage appearing across the bit lines BL1 and BL2 to a sense amplifier not illustrated as an output.
Next, a description will be given of the operation of the bipolar memory in the case of reading and writing cell information from and to the cell S11, together with reference to FIG. 2.
When reading cell information from the cell S11, a chip select signal SG1 having the level L is supplied to an input terminal CS indicating the selection of the chip. In response to the level L at the input terminal CS, a transistor Tr10 connected to the input terminal CS via a current switch circuit KS1 and an input transistor Tr9 produces an output having the level L, and the operation of the sense amplifier is enabled. At the same time, an address signal addressing the cell S11 is outputted from the address decoder 3 and the logic level of the word line WL1 is set to the level H. Further, a signal having the level H is supplied to the input terminal BS1 from the column decoder corresponding to the column C1, and thereby the cell S11 is specified in combination with the word line WL1.
In the case in which the logic level of the chip select signal SG1 is set to the level H, on the other hand, the transistor Tr10 connected to the sense amplifier not illustrated produces an output of the level H, and in response thereto, the output of the sense amplifier is shut off. In order to control the operation of the transistor Tr10 in response to the signal SG1 at the input terminal CS, an intermediate voltage between the level H and the level L is applied to an input terminal VBB1 constantly as a reference for discriminating the level of the signal SG1. The foregoing operation and construction are well known and thus, further description will be omitted.
Further, a write control signal SG2 is supplied to an input terminal WE with a level H, as shown in FIG. 2, indicating reading of information, in addition to and in synchronization with the chip select signal SG1 of the level L. In response thereto, a transistor 14 to which the signal SG1 is supplied after passing through a transistor Tr12 and a current switch K2 is controlled such that an emitter level thereof is set to a level H. To an input terminal VBB2, a voltage identical to the foregoing reference voltage to the input terminal VBB1 is applied as a reference for discriminating the level of the signal applied to the terminal WE.
When the emitter level of the transistor Tr14 is set to the level H in response to the write control signal SG2 having the level of L, transistors Tr15, Tr16 and Tr17 constituting a write amplifier part 4 are all turned on. In response thereto, transistors Tr18, Tr19, Tr20 and Tr21 are turned off irrespective of the input signal to a data input terminal DA of the write amplifier part 4. Further, in response to the turning off of the transistors Tr18, Tr19, Tr20 and Tr21, the emitter level of the transistors Tr22 and Tr23 are set at the level H. This in turn causes the turning on of transistors Tr24 and Tr25.
The transistor Tr24 has an emitter connected to the emitter of the transistor Tr3 used for selection of the bit line BL2, and the transistor Tr25 has an emitter which is connected to the emitter of the transistor Tr1 which is used for selection of the bit line BL1. It will be noted that the base voltage applied to the base of the transistors Tr24 and Tr25 is set higher than the corresponding base voltage of the transistors Tr1 and Tr2. Thus, when the transistors Tr24 and Tr25 are turned on, the transistors Tr1 and Tr3 are turned off. Further, a reference voltage having a level identical to that of the reference voltage supplied to the input terminals VBB1 and VBB2 is supplied to input terminals VBB3 and VBB4 continuously as a reference for discriminating the state of input data supplied to an input terminal DA. A description of this operation for discriminating the logic level of the input data to the terminal DA will be omitted as the construction thereof is well known and the operation thereof is not related to the subject matter of the present invention except that the input data is supplied to the transistors Tr18, Tr19, Tr20 and Tr20 and controls the state of the transistors Tr26 and Tr27 in addition to the write control signal at the input terminal WE.
In the state described heretofore, transistors Tr26 and Tr27 are further turned on in response to the turning on of the transistor Tr15, and these transistors Tr26 and Tr27 assume an unsaturated state because of provision of the resistors R1 and R2 and diodes D1 and D2. The transistors Tr26 and Tr27 have respective emitters which supply voltage from the respective emitters to the base of the transistor Tr5 connected to the bit line BL1 and to the base of the transistor Tr6 in response to the base voltage supplied thereto with a level variable between the level H and the level L. When the level of the write control signal SG2 is the level L, the emitter voltage at the transistors Tr26 and Tr27 has an identical level intermediate between the level H and the level L.
Thus, in the case where the cell S11 is selected and the cell information stored therein is to be read out, the transistors Tr2 and Tr4 are turned on in response to the signal of the level H to the input terminal BS while transistors Tr1 and Tr3 are turned off in response to the turning on of the transistors Tr24 and Tr25 which in turn is caused by the level H of the write control signal SG2 to the input terminal WE. When the transistor (not shown) in the cell S11 at the side of the bit line BL1 is in the turned-on state, a current IR flows from the word line WL1 through the cell S11, the bit line BL1 and the transistor Tr2. As a result, the logic level of the bit line BL1 changes to the level H. Further, the read current IR flows through the bit line BL2 and further through the transistor Tr4 from the transistor Tr6 which is turned on in response to the operation of the transistors Tr26 and Tr27 in the write amplifier 4 as already described, and thereby the logic level of the bit line BL2 is set to the level L. The voltage difference across the bit lines BL1 and BL2 is detected by the transistors Tr7 and Tr8 and supplied to the sense amplifier.
When writing cell information, the write control signal SG2 is set to the level L as shown in FIG. 2, and the voltage at a node A in the write amplifier 4 changes to the level L in response to the signal SG2 to the input terminal WE which now has the logic level L. In response thereto, one of the transistors Tr24 and Tr25 is turned on while the other is turned off, depending on whether the signal supplied to an input terminal DA has the logic level H or L.
Thus, when writing information to the cell S11 at the side of the bit line BL1, signals having the level H are supplied to the respective bases of the transistors Tr24 and Tr27, and signals having the level L are supplied to the respective bases of the transistors Tr25 and Tr26. In response thereto, the transistors Tr1, Tr2, Tr4 and Tr6 are turned on while the transistors Tr3 and Tr5 are turned off, and a write current IR+IW flows through the bit line BL1 from the word line WL1 and the cell S11 and a write current IR flows through the bit line BL2 from the transistor Tr6.
By constructing the memory as described above, a write current IR+IW which is substantially larger than the read current IR flows through the addressed cell S11 at the time of writing, and thereby it becomes possible to decrease the time needed to turn off the transistor at the side of the bit line BL2 and to turn on the transistor at the side of the bit line BL1.
In the bipolar random access memory, the writing speed is increased by increasing write current IR+IW. It should be noted, however, that such a bipolar random access memory has a construction wherein a large number of bit lines are connected to each of the word lines and thus a very large current flows through the word line when writing is carried out simultaneously in a number of bit lines. When such large current flows, an unacceptable voltage drop may occur in the address decoder 3 which eventually leads to a failure to provide a sufficient level of voltage for the logic level H or disconnection of the word line. Thus, there has been a limitation regarding the write current in the prior art bipolar random access memory, and associated therewith, a limitation regarding the writing speed in such a memory.